Individual semiconductor devices are miniaturized more and more with the progress of the working technology of the semiconductor integrated circuit (LSI). Also, the higher density, increase in the layer number, and reduction in the layer thickness of the wiring in LSI are accelerated, and thus the stress applied to the wiring and the density of the current that flows through the wiring are steadily increased respectively. Therefore, if the high-density current is supplied to the wiring, the breaking phenomenon of the wiring, which is called the electromigration (EM), for example, is ready to occur. It is considered that, since the metal atoms are moved/diffused due to the collision of the high-density electron current, a driving force of the electromigration is caused. Because the deterioration phenomenon caused due to the electromigration becomes intensified more and more with the miniaturization of the device, the wiring material and the wiring structure with the higher reliability, through which the current with higher density can be supplied, must be developed
In the semiconductor device, the copper wiring is employed as the wiring in which the electromigration is difficult to occur rather than the aluminum wiring.
As the method of forming the copper wiring, the damascene method having the step of burying the copper in the trench formed in the interlayer insulating film is put in practical use. Also, the dual-damascene method for forming the via hole under the trench to form the via and the wiring simultaneously is known. It is the mainstream that, prior to bury the copper in such trench and such via hole, the barrier layer and the copper seed layer are formed as the underlying layer of the copper by the sputter method. The barrier layer is used to prevent the diffusion of copper and serves as a part of the wiring or the plug. Also, the copper seed layer is formed to promote the growth of the copper film.
Meanwhile, in the generation of the 0.1 μm rule device, it is considered that a diameter of the via hole formed under the wiring is reduced up to about 0.15 μm and also it is supposed that the aspect ratio exceeds 5.
In the case that the fine via and wiring are formed of copper, if it is tried to form the barrier layer and the copper seed layer in the via hole and the trench by the sputter, following problems are caused.
First, good coverage cannot be obtained by the sputter method. Therefore, if the barrier layer is to be formed in the fine via hole, for example, the barrier layer having a film thickness that is considerably thicker than that required of the side wall of the via hole must be formed on the insulating film around the via hole. As a result, if the wiring is formed by the dual-damascene method, a rate of the barrier layer in a sectional area of the trench becomes large. Since the material used as the barrier layer has a high resistance normally, the resistance of the overall wiring is increased if an occupied rate of the barrier layer in the wiring is increased, and thus the merit that the copper wiring having the low resistance is used is eliminated. Also, if the barrier layer formed on the bottom of the via hole becomes thick, the contact resistance is increased in the via hole.
Second, the sputter method has its limit on the coverage. Therefore, overhang such that the copper seed layer is formed to block slightly the opening of the fine via hole, lack of the coverage caused on the side wall of the via hole, and aggregation of the copper seed layer are generated. Thus, it is difficult to bury perfectly the copper in the via hole by the later electrolytic plating.
Accordingly, in order to respond to the further miniaturization in the future, the thin barrier layer and the copper seed layer must be formed by the CVD method that has the good coverage.
However, if the barrier layer made of titanium nitride (TiN) is formed by the CVD method employing tetrakis(diethylamino)titanium (Ti{N(C2H5)}4: TDEAT), it is difficult to reduce the resistance lower than 500 μΩcm.
Also, if the barrier layer is formed by using TDEAT only, the coverage of the via hole is good, but the porous barrier layer containing the carbon impurity is formed. In contrast, if NH3 is added by a minute amount in forming such barrier layer, the film quality is improved and also the low-resistance film containing the small carbon impurity can be formed. But the good coverage cannot be obtained.
In the existing condition, the film resistance of the barrier layer formed under the condition that the coverage of more than 35% can be obtained at the via bottom is about 500 μΩcm. In order to reduce sufficiently the resistance of the via chain or the overall wiring, the barrier film having the bottom coverage of more than 50% and less than 300 μΩcm is required.
Also, if the TiN barrier layer and the copper seed layer are formed by the present CVD technology, the adhesion between these layers becomes insufficient. Therefore, these layers cannot stand the thermal stress applied in forming the multi-layered wiring structure, or the mechanical stress applied by chemically mechanically polishing (CMP) the unnecessary copper seed layer and barrier layer, etc., and thus the copper seed layer peels off easily from the barrier layer. As a result, that is not put to practical use.